1. Field of the Invention
The present invention particularly relates to improvements in automatic writing and erasure functions of a semiconductor memory circuit capable of electrically writing and erasing data.
2. Description of the Related Art
Conventionally, a semiconductor memory, e.g., a flash EEPROM has three basic modes, i.e., a writing mode, an erasure mode, and a reading mode.
FIG. 1 is a flow chart showing a so-called automatic writing mode as a variation of the writing mode.
This automatic writing mode will be briefly explained as follows.
At first, address data and input data are inputted into a memory circuit (in a step ST1), and the input data is written into memory cells designated by the address data (in a step ST2).
After a recovery time in which a high voltage to be applied to the memory cell is discharged (in a step ST3), the memory is brought into a verify mode in which a threshold value of the memory cell is verified by a sensing amplifier (in a step ST4).
Output data of sensing amplifiers and the input data of the memory circuit are compared with each other by a comparator. If both of the data are equal to each other, writing of the input data is regarded as completed. If both of the data are not equal to each other, re-writing of the input data is carried out (in steps ST5 to ST7).
Re-writing of input data can be performed for up to twenty-five times, and if both of output and input data are not then equal to each other, the memory circuit itself is determined as defective.
Thus, in an automatic writing mode, after desired data is written into memory cells, threshold values of the memory cells are read out by sensing amplifiers, and determination is automatically made as to whether the desired data has been properly written. If desired data has not been properly written into the memory cell, writing of the data is repeated until the desired data is properly written.
An automatic erasure mode is also used in addition to the automatic writing mode. In an automatic erasure mode, after data in memory cells is erased, threshold values of the memory cells are read by sensing amplifiers, and determination is automatically made as to whether or not the data in the memory cells has been properly erased. If the data in the memory cells have not been properly erased, erasure of the data is repeated until the data in the memory cells are properly erased.
(1) Conventional circuit A
FIGS. 2 to 4 show an example of a conventional circuit. FIG. 3 is a circuit diagram showing the structure of a sensing amplifier shown in FIG. 2, and FIG. 4 is a circuit diagram showing the structure of a comparator shown in FIG. 2.
A write (or erase) circuit 17 receives a write (or erase) start signal PSTART, and performs writing or erasure of data with respect to predetermined main cells (memory cells) MC of a memory cell array 11. When verifying data, determination is made as to whether or not predetermined data has been properly written into the main cells MC.
Firstly, data in those memory cells MC into which data have already been written is read out by sensing amplifiers 12-1 to 12-N.
The sensing amplifiers 12-1 to 12-N adopt a method of comparing a cell current of a main cell MC with a cell current of a reference cell RC. A cell current depends on a word line potential (or gate potential) VWL and a threshold value Vth of each main cell.
If a word line potential is kept constant, a main cell MC is turned off when the threshold value Vth is sufficiently high, and a cell current therefore does not flow through the main cell MC. Therefore, the drain potential of a transistor P1 becomes higher than the drain potential VREF of a transistor P2. That is, a sensing amplifier output data "0".
On the other hand, a main cell MC is turned on when the threshold value of the main cell MC is sufficiently low, and a cell current flow through the main cell MC. Therefore, the drain potential VSA of the transistor P1 becomes lower than the drain current VREF of the transistor P2. That is, a sensing amplifier output data "1".
In this memory circuit, the word line potential VWL is set to 7 V during verification in an automatic writing mode (only where data "0" is written), while the word line potential VWL is set to 3 V during verification in an automatic erasure mode (in which all the data are set to "0"). Thus, the word line potential VWL during verification in these modes has a difference of .+-.2 V from the word line potential VWL (=5 V) when data is normally read out.
This difference is set such that the sensing amplifiers easily output data "1" during verification in the automatic writing mode (only where data "0" is written) and easily output data "0" during verification in the automatic erasure mode, in order to determine completion of writing or erasure put under stricter conditions, and to thereby achieve perfect writing and erasure of data.
Secondly, the input data (i.e., write data or erase data) DIN and output data of the sensing amplifiers SA are compared with each other by comparators 13-1 to 13-N.
Output data of the comparator 13-1 is inputted into an input terminal of an NOR circuit 14-1. Data "0" is inputted into another input terminal of the NOR circuit 14-1. Output data of the NOR circuit 14-1 is inputted into an inverter 15-1.
Output data of the comparator 13-2 is inputted into an input terminal of an NOR circuit 14-2. Output data of an inverter 15-1 is inputted into another input terminal of the NOR circuit 14-2. Output data of the NOR circuit 14-2 is inputted into an inverter 15-2.
In the same way, output data of a comparator 13-N (where N is a natural number) is inputted into an input terminal of an NOR circuit 14-N. Output data of an inverter 15-(N-l) is inputted into another input terminal of the NOR circuit 14-N. Output data of the NOR circuit 14-N is inputted into an inverter 15-n.
Then, output data B of the inverter 15-N is inputted into a determination circuit 16, and the determination circuit 16 determine whether or not desired data has been written into N pieces of main cells.
Specifically, if at least one of N comparators outputs data indicating incomplete writing or incomplete erasure (e.g., data "1"), output data B of the inverter 15-N is "1". Therefore, a determination circuit 16 determines that writing or erasure with respect to main cells is not completed, and sends a write incomplete (or erase incomplete) signal PNO to a re-write (or re-erase) signal generator circuit 30.
The re-write (or re-erase) signal generator circuit 30 receives the write incomplete (or erase incomplete) signal PNO, and sends a re-write (or re-erase) signal PRETRY to a write (or erase) circuit 17.
Then, the write (or erase) circuit 17 receives the re-write (or re-erase) signal PRETRY, and performs re-writing or re-erasure of data with respect to predetermined main cells MC of the memory cell 11.
Thereafter, verification is performed in the same way as explained above, and if verification is repeated for a predetermined number of times (e.g., twenty-five times), the re-write (or re-erase) signal generator circuit 30 generates a signal indicating a defective product without sending a re-write (or re-erase) signal PRETRY to the write (or re-erase) circuit 17.
Meanwhile, if all of the comparators output data indicating completion of writing or erasure (i.e., data "0"), the output data of the inverter 15-N is "0". Therefore, the determination circuit 16 determines that writing or erasure has been completed with respected to main cells, and outputs a signal indicating a valid product, without sending a write-incomplete (or erase-incomplete) signal PNO to the re-write (or re-erase) signal generator circuit 30.
(2) Conventional circuit B
FIGS. 5 and 6 show another example of a conventional circuit for executing an automatic writing (or erasing) mode. In addition, FIG. 6 is a circuit diagram showing the structure of a clocked inverter shown in FIG. 5.
This circuit has the same structure as the conventional circuit shown in FIG. 2, except for that a 10 clocked inverter 18 is connected between an inverter 15-N and a determination circuit 16.
The clocked inverter 18 is controlled in accordance with a control signal CTL1. While the control signal CTL1 is "1", the clocked inverter 18 maintains the conditions of data B which is obtained when the control signal CTL1 becomes "1", and outputs the data as output data B', as is shown in FIG. 7.
In case of a conventional circuit A, if the output data B is inverted to "1" from "0" in an operation determination range due to some reasons, the determination circuit 16 firstly determines that writing or erasure has been completed with respect to main cells, and then determines that writing or erasure is incomplete before the end of the range. The determination circuit 16 thus sends both of a re-write (or re-erase) signal PNO and a signal (PGOK) indicating completion of writing or erasure to the re-write (or re-erase) signal generator circuit 30, which cause an erroneous operation.
In case of a conventional circuit B, such an erroneous operation as shown in a conventional circuit A is prevented since an input B' is fixed to "0" or "1" when the control signal CTL1 is "1" (i.e., during an operational determination range).
However, operation in the automatic writing (or erasure) mode is arranged such that the threshold value Vth of main cells is raised or lowered every time when writing or erasure is repeated.
Therefore, during verification in an automatic writing mode (only where data "0" is written), a sensing amplifiers is subjected to a change that a relation of VSA&lt;Vref changes to a relation of VSA&gt;Vref, i.e., the output of the sensing amplifier changes to "0" from "1".
Further, during verification in an automatic erasure mode, a relation of VSA&gt;Vref changes to VSA&lt;Vref in a sensing amplifier, i.e., the sensing amplifiers are subjected to a change that the output thereof changes from "0" to "1".
Thus, in the way in which the output of a sensing amplifier changes from "1" to "0" or from "0" to "1", there must be a phase in which VSA is equal to Vref. In this phase, the output of the sensing amplifier is so unstable that the sensing amplifier is brought into an oscillating condition, i.e., alternately outputs data "0" and data "1".
When the output of the sensing amplifier thus oscillates, the output of a comparator naturally oscillates. In this case, since determination as to whether writing (or erasure) has been completed or is incomplete is made at the instance when the control signal CTL1 in the clocked converter changes from "0" to "1", determination indicating complete writing (or erasure) may be made at a certain probability, or determination indicating incomplete writing (or erasure) may be made at a certain provability, as shown in FIGS. 10 and 11, even though the threshold value of main cells is substantially equal to that of a reference cell.
Therefore, for example, in an automatic writing mode, determination that data writing has been completed is made even when the relation of VSA&gt;Vref is not satisfied, and leads to a problem that writing of data is insufficient. On the other hand, there simultaneously exist several main cells which satisfy the relation of VSA&gt;Vref. This results in a problem that a distribution of threshold values Vth of main cells is broadened after completion of data writing.